GD32V Porting Guide

Mon, 01 Jan 0001 00:00:00 +0000

Overview

GD32V-related code:

Architecture Description Layer (ADL): XWOS/xwcd/soc/riscv/nuclei/gcc
CPU Description Layer (CDL): XWOS/xwcd/soc/riscv/nuclei/gcc/bumblebee
SoC Description Layer (SDL)
- GD32V: XWOS/xwcd/soc/riscv/nuclei/gcc/bumblebee/gd32v

Uses non-vectored mode, unified entry: XWOS/xwcd/soc/riscv/nuclei/gcc/bumblebee/gd32v/soc.S: soc_isr_entry
Uses the RISC-V standard register mscratch to implement a dual-stack working mode similar to ARM-Cortex-M
Unified exception entry: XWOS/xwcd/soc/riscv/nuclei/gcc/bumblebee/gd32v/soc.S: soc_esr_entry
Source code:
- XWOS/xwcd/soc/riscv/nuclei/gcc/bumblebee/gd32v/xwosimpl_soc_irq.h
- XWOS/xwcd/soc/riscv/nuclei/gcc/bumblebee/gd32v/xwosimpl_irq.h
- XWOS/xwcd/soc/riscv/nuclei/gcc/bumblebee/gd32v/xwosimpl_irq.c
- XWOS/xwcd/soc/riscv/nuclei/gcc/bumblebee/gd32v/soc.S

Source code:
- XWOS/xwcd/soc/riscv/nuclei/gcc/bumblebee/gd32v/xwosimpl_skd.h
- XWOS/xwcd/soc/riscv/nuclei/gcc/bumblebee/gd32v/xwosimpl_skd.c
- XWOS/xwcd/soc/riscv/nuclei/gcc/bumblebee/gd32v/xwosasmimpl_skd.S

RISC-V requires the stack to be 16-byte aligned;
RISC-V only uses full descending stacks;
RISC-V ABI documents divide registers into two types: caller-saved (i.e., volatile) and callee-saved (i.e., non-volatile).

When entering an interrupt from a thread, the interrupt entry routine automatically saves caller-saved registers to the stack: