SoC Porting
18 minute read
Overview
XWOS porting involves the following steps:
- Build environment
- Initialization flow
- XWOS Porting Layer (XWOSPL)
- XWOS Porting Implementation Layer (XWOSIMPL)
The XWOS Porting Layer (XWOSPL) defines interfaces, while the XWOS Porting Implementation Layer (XWOSIMPL) provides implementations.
To improve code reusability, the code related to the XWOS Porting Implementation Layer (XWOSIMPL) is further subdivided into:
- Architecture Description Layer (ADL)
- CPU Description Layer (CDL)
- SoC Description Layer (SDL)
- Board Description Layer (BDL)
For example, under the ARMv7m architecture, the ADL directory is xwcd/soc/arm/v7m/gcc/. The code within is
reused for STM32, S32K, i.MX RT1052, GD32, etc. Differences between m3, m4, and m7 are described by the CDL directory.
Different SoCs with the same CPU core are described by SDL. Different boards are described by BDL. Together they complete
the implementation of the build environment, initialization flow, and the XWOS Porting Implementation Layer (XWOSIMPL).
XWOS Porting Layer (XWOSPL) Header File Rules
xwos/ospl/*.h: Header files provided by XWOS to the BSP, must not be included by XWOS’s own header files.- Prefix
xwospl: Functions that the BSP must implement - Prefix
xwosplcb: Functions that can be called by the BSP
- Prefix
xwos/ospl/*.h: Contains header files provided by the BSP to XWOS, can be included by XWOS’s header files.xwos/ospl/type.h: Contains platform type definitionsxwos/ospl/compiler.h: Contains platform compiler-related definitionsxwos/ospl/isa.h: Contains platform instruction and architecture-related definitionsxwos/ospl/lfq.h: Contains lock-free queue-related definitionsxwos/ospl/setjmp.h: Containssetjmp.h-related definitionsxwos/ospl/spinlock.h: Contains spinlock-related definitionsxwos/ospl/xwaop[bit].h: Contains atomic operation-related definitionsxwos/ospl/xwbmpaop.h: Contains bitmap atomic operation-related definitionsxwos/ospl/xwbop.h: Contains bit operation-related definitionsxwos/ospl/xwsc.h: Contains system call-related definitions
Porting
XWOS porting includes: basic types, compiler, breakpoints, setjmp, system calls and system privilege, bit operations, atomic operations, lock-free queues, spinlocks, interrupts, hardware timers, and scheduler.
Basic Types
XWOS defines its own set of basic types, around which all source code is built.
- XWOS header file:
xwos/lib/type.h, see Basic Types for details. - Interface:
xwos/ospl/type.h - Implementation: The file
xwosimpl_soc_type.hredefines certain types according to the architecture’s ELF ABI rules, and the macroARCH_HAVE_xxxxmust be defined as 1, indicating that the default definition ofxxxxis overridden. This file is generally located in the ADL directory, e.g.,xwcd/soc/arm/v7m/gcc/xwosimpl_soc_type.h. - Basic types:
ARCH_HAVE_XWU8_T: Macro, defined as 1 indicates that typexwu8_tis provided inarch_type.hxwu8_t: Type, 8-bit unsigned integerARCH_HAVE_ATOMIC_XWU8_T: Macro, defined as 1 indicates that typeatomic_xwu8_tis provided inarch_type.hatomic_xwu8_t: Type, atomic 8-bit unsigned integerARCH_HAVE_XWS8_T: Macro, defined as 1 indicates that typexws8_tis provided inarch_type.hxws8_t: Type, 8-bit signed integerARCH_HAVE_ATOMIC_XWS8_T: Macro, defined as 1 indicates that typeatomic_xws8_tis provided inarch_type.hatomic_xws8_t: Type, atomic 8-bit signed integerARCH_HAVE_XWU16_T: Macro, defined as 1 indicates that typexwu16_tis provided inarch_type.hxwu16_t: Type, 16-bit unsigned integerARCH_HAVE_ATOMIC_XWU16_T: Macro, defined as 1 indicates that typeatomic_xwu16_tis provided inarch_type.hatomic_xwu16_t: Type, atomic 16-bit unsigned integerARCH_HAVE_XWS16_T: Macro, defined as 1 indicates that typexws16_tis provided inarch_type.hxws16_t: Type, 16-bit signed integerARCH_HAVE_ATOMIC_XWS16_T: Macro, defined as 1 indicates that typeatomic_xws16_tis provided inarch_type.hatomic_xws16_t: Type, atomic 16-bit signed integerARCH_HAVE_XWU32_T: Macro, defined as 1 indicates that typexwu32_tis provided inarch_type.hxwu32_t: Type, 32-bit unsigned integerARCH_HAVE_ATOMIC_XWU32_T: Macro, defined as 1 indicates that typeatomic_xwu32_tis provided inarch_type.hatomic_xwu32_t: Type, atomic 32-bit unsigned integerARCH_HAVE_XWS32_T: Macro, defined as 1 indicates that typexws32_tis provided inarch_type.hxws32_t: Type, 32-bit signed integerARCH_HAVE_ATOMIC_XWS32_T: Macro, defined as 1 indicates that typeatomic_xws32_tis provided inarch_type.hatomic_xws32_t: Type, atomic 32-bit signed integerARCH_HAVE_XWU64_T: Macro, defined as 1 indicates that typexwu64_tis provided inarch_type.hxwu64_t: Type, 64-bit unsigned integerARCH_HAVE_ATOMIC_XWU64_T: Macro, defined as 1 indicates that typeatomic_xwu64_tis provided inarch_type.hatomic_xwu64_t: Type, atomic 64-bit unsigned integerARCH_HAVE_XWS64_T: Macro, defined as 1 indicates that typexws64_tis provided inarch_type.hxws64_t: Type, 64-bit signed integerARCH_HAVE_ATOMIC_XWS64_T: Macro, defined as 1 indicates that typeatomic_xws64_tis provided inarch_type.hatomic_xws64_t: Type, atomic 64-bit signed integerARCH_HAVE_XWSZ_T: Macro, defined as 1 indicates that typexwsz_tis provided inarch_type.hxwsz_t: Type, unsigned size value typeARCH_HAVE_ATOMIC_XWSZ_T: Macro, defined as 1 indicates that typeatomic_xwsz_tis provided inarch_type.hatomic_xwsz_t: Type, atomic unsigned size value typeARCH_HAVE_XWSSZ_T: Macro, defined as 1 indicates that typexwssz_tis provided inarch_type.hxwssz_t: Type, signed size value typeARCH_HAVE_ATOMIC_XWSSZ_T: Macro, defined as 1 indicates that typeatomic_xwssz_tis provided inarch_type.hatomic_xwssz_t: Type, atomic signed size value typeARCH_HAVE_XWSTK_T: Macro, defined as 1 indicates that typexwstk_tis provided inarch_type.hxwstk_t: Type, unsigned stack typeARCH_HAVE_ATOMIC_XWSTK_T: Macro, defined as 1 indicates that typeatomic_xwstk_tis provided inarch_type.hatomic_xwstk_t: Type, atomic unsigned stack typeARCH_HAVE_XWPTR_T: Macro, defined as 1 indicates that typexwptr_tis provided inarch_type.hxwptr_t: Type, unsigned pointer value typeARCH_HAVE_ATOMIC_XWPTR_T: Macro, defined as 1 indicates that typeatomic_xwptr_tis provided inarch_type.hatomic_xwptr_t: Type, atomic unsigned pointer value typeARCH_HAVE_XWREG_T: Macro, defined as 1 indicates that typexwreg_tis provided inarch_type.hxwreg_t: Type, unsigned register typeARCH_HAVE_ATOMIC_XWREG_T: Macro, defined as 1 indicates that typeatomic_xwreg_tis provided inarch_type.hatomic_xwreg_t: Type, atomic unsigned register typeARCH_HAVE_XWSREG_T: Macro, defined as 1 indicates that typexwsreg_tis provided inarch_type.hxwsreg_t: Type, signed register typeARCH_HAVE_ATOMIC_XWSREG_T: Macro, defined as 1 indicates that typeatomic_xwsreg_tis provided inarch_type.hatomic_xwsreg_t: Type, atomic signed register typeARCH_HAVE_XWSQ_T: Macro, defined as 1 indicates that typexwsq_tis provided inarch_type.hxwsq_t: Type, unsigned sequence value typeARCH_HAVE_ATOMIC_XWSQ_T: Macro, defined as 1 indicates that typeatomic_xwsq_tis provided inarch_type.hatomic_xwsq_t: Type, atomic unsigned sequence value typeARCH_HAVE_XWSSQ_T: Macro, defined as 1 indicates that typexwssq_tis provided inarch_type.hxwssq_t: Type, signed sequence value typeARCH_HAVE_ATOMIC_XWSSQ_T: Macro, defined as 1 indicates that typeatomic_xwssq_tis provided inarch_type.hatomic_xwssq_t: Type, atomic signed sequence value typeARCH_HAVE_XWID_T: Macro, defined as 1 indicates that typexwid_tis provided inarch_type.hxwid_t: Type, unsigned ID value typeARCH_HAVE_ATOMIC_XWID_T: Macro, defined as 1 indicates that typeatomic_xwid_tis provided inarch_type.hatomic_xwid_t: Type, atomic unsigned ID value typeARCH_HAVE_XWSID_T: Macro, defined as 1 indicates that typexwsid_tis provided inarch_type.hxwsid_t: Type, signed ID value typeARCH_HAVE_ATOMIC_XWSID_T: Macro, defined as 1 indicates that typeatomic_xwsid_tis provided inarch_type.hatomic_xwsid_t: Type, atomic signed ID value typeARCH_HAVE_XWER_T: Macro, defined as 1 indicates that typexwer_tis provided inarch_type.hxwer_t: Type, signed error code typeARCH_HAVE_ATOMIC_XWER_T: Macro, defined as 1 indicates that typeatomic_xwer_tis provided inarch_type.hatomic_xwer_t: Type, atomic signed error code typeARCH_HAVE_XWPR_T: Macro, defined as 1 indicates that typexwpr_tis provided inarch_type.hxwpr_t: Type, signed priority typeARCH_HAVE_ATOMIC_XWPR_T: Macro, defined as 1 indicates that typeatomic_xwpr_tis provided inarch_type.hatomic_xwpr_t: Type, atomic signed priority typeARCH_HAVE_XWBMP_T: Macro, defined as 1 indicates that typexwbmp_tis provided inarch_type.hxwbmp_t: Type, unsigned bitmap typeARCH_HAVE_ATOMIC_XWBMP_T: Macro, defined as 1 indicates that typeatomic_xwbmp_tis provided inarch_type.hxwbmpy_a: Type, atomic unsigned bitmap typeARCH_HAVE_XWTM_T: Macro, defined as 1 indicates that typexwtm_tis provided inarch_type.hxwtm_t: Type, signed priority typeARCH_HAVE_ATOMIC_XWTM_T: Macro, defined as 1 indicates that typeatomic_xwtm_tis provided inarch_type.hatomic_xwtm_t: Type, atomic signed priority typeARCH_HAVE_XWLFQ_T: Macro, defined as 1 indicates that typexwlfq_tis provided inarch_type.hxwlfq_t: Type, lock-free queue typeARCH_HAVE_ATOMIC_XWLFQ_T: Macro, defined as 1 indicates that typeatomic_xwlfq_tis provided inarch_type.hatomic_xwlfq_t: Type, atomic lock-free queue typeARCH_HAVE_XWISR_F: Macro, defined as 1 indicates that typexwisr_fis provided inarch_type.hatomic_xwer_t: Type, atomic signed error code typeARCH_HAVE_XWIRQ_T: Macro, defined as 1 indicates that typexwirq_tis provided inarch_type.hxwirq_t: Type, signed interrupt number type
Compiler
- XWOS header file:
xwos/lib/compiler.h, included byxwos/standard.h. - Interface:
xwos/ospl/compiler.h - Implementation:
xwosimpl_soc_compiler.h
Compiler-related macro definitions:
__xwcc_section(s): Indicates that a symbol belongs to sections.__xwcc_aligned(x): Indicates that data’s starting address is aligned to x bytes.__xwcc_inline: Indicates that a function is inline, must be used together withstatic.__xwcc_packed: Indicates that a data structure is densely packed, and the compiler should not perform alignment optimization.__xwcc_must_check: Indicates that the function’s return value must be read, otherwise the compiler will issue a warning.__xwcc_unused: Indicates that a variable or function is unused, used to suppress compiler warnings.__xwcc_noreturn: Indicates that a function will not return.__xwcc_hot: Indicates that a function is frequently called in the code, which may help some compilers optimize compilation.__xwcc_atomic: Indicates that a variable is atomic. Defined as _Atomic in the C11 standard, and as volatile in the C99 standard.__xwcc_likely(x): Indicates that conditionxis likelytrue, used forif..else..optimization.__xwcc_unlikely(x): Indicates that conditionxis likelyfalse, used forif..else..optimization.__xwcc_alignl1cache: Indicates that data’s starting address is aligned to the L1 cache (way-set cache) cache line.__xwcc_alignptr: Indicates that data’s starting address is aligned to the pointer size.xwcc_offsetof(type, member): Calculates the offset of member within the structure type, equivalent tooffsetof()in the standard C library.
Architecture Instructions
The CPU architecture provides some special instructions that are generally difficult to express in C language for convenient use. XWOS kernel provides the same encapsulation for unified parts.
- XWOS header file: Included in
xwos/standard.h. - Interface:
xwos/ospl/isa.h - Implementation:
xwosimpl_soc_isa.h
These architecture instructions include but are not limited to:
- Breakpoint instruction
- Memory barrier
setjmp/longjmp
XWOS’s C library provides a function combination similar to setjmp()/longjmp() from the C standard library.
Its implementation is closely related to how registers are saved during context switching.
- XWOS header file:
xwos/lib/setjmp.h - Interface:
xwos/ospl/setjmp.h - Implementation:
xwosimpl_soc_setjmp.h
System Calls and System Privilege
CPUs typically have two privilege modes: user and system.
- In system mode, all registers can be accessed;
- In user mode, certain internal CPU registers cannot be accessed (e.g., interrupt enable/disable), and can only be accessed through special instructions that switch the CPU to system mode.
XWOS’s C library provides the function xwsc() for switching CPU access privilege, allowing user mode to temporarily have system privilege to call a function.
- XWOS header file:
xwos/lib/sc.h - Interface:
xwos/ospl/xwsc.h - Implementation:
xwosimpl_soc_xwsc.h
Bit Operations
XWOS’s C library provides a function set for bit operations. To improve efficiency, some bit operations can be implemented using special instructions.
- XWOS header file:
xwos/lib/xwbop.h - Interface:
xwos/ospl/xwbop.h - Implementation:
xwosimpl_soc_xwbop.h - Basic type bit operation function sets:
- Bit order mirroring: Intel bit order (mainstream little-endian CPUs use Intel bit order) has higher bits with larger bit numbers.
Motorola bit order (PowerPC architecture CPUs) has higher bits with smaller bit numbers.
Therefore, when mixing the two systems, data bit order must be mirrored.
xwbop_rbit8(): Mirror the bit order of 8-bit dataxwbop_rbit16(): Mirror the bit order of 16-bit dataxwbop_rbit32(): Mirror the bit order of 32-bit dataxwbop_rbit64(): Mirror the bit order of 64-bit data
- Endian reversal:
xwbop_re16(): Reverse the byte order of 16-bit dataxwbop_re16s32(): Reverse the byte order of 16-bit data, sign-extend to 32 bits, return signed 32-bit dataxwbop_re32(): Reverse the byte order of 32-bit dataxwbop_re32s64(): Reverse the byte order of 32-bit data, sign-extend to 64 bits, return signed 64-bit dataxwbop_re64(): Reverse the byte order of 64-bit data
- Find set bits:
xwbop_ffs8(): 8-bit data, search from the least significant bitxwbop_fls8(): 8-bit data, search from the most significant bitxwbop_ffs16(): 16-bit data, search from the least significant bitxwbop_fls16(): 16-bit data, search from the most significant bitxwbop_ffs32(): 32-bit data, search from the least significant bitxwbop_fls32(): 32-bit data, search from the most significant bitxwbop_ffs64(): 64-bit data, search from the least significant bitxwbop_fls64(): 64-bit data, search from the most significant bit
- Bit order mirroring: Intel bit order (mainstream little-endian CPUs use Intel bit order) has higher bits with larger bit numbers.
Motorola bit order (PowerPC architecture CPUs) has higher bits with smaller bit numbers.
Therefore, when mixing the two systems, data bit order must be mirrored.
Atomic Operations
XWOS’s C library provides a function set for atomic operations. The implementation of atomic operations depends on the CPU’s atomic operation instructions.
- XWOS header files:
xwos/lib/xwaop.h
- Interface:
xwos/ospl/xwaop.h
- Implementation:
xwosimpl_soc_xwaop.hxwosimpl_soc_xwaop/*
- Description:
- Other types of atomic operations will be wrapped by the XWOS kernel based on 4 basic types. 64-bit atomic operations may not be provided if unsupported;
- If the CPU architecture is relatively simple and lacks atomic operation instructions, these atomic operation functions can be implemented by disabling interrupts;
- Some CPU architectures only provide atomic operation instructions that match the CPU bit width. For code portability, it is best to use only atomic data types that match the CPU bit width;
- Basic type atomic operation function sets:
load(): Load (memory order specifiable)store(): Store (memory order specifiable)read(): Read (memory order: load-acquire)write(): Write (memory order: store-release)add(): Additionsub(): Subtractionrsb(): Reverse subtractionand(): AND operationor(): OR operationxor(): XOR operationteq_then_write(): Test if equal to test value, then writeteq_then_add(): Test if equal to test value, then addteq_then_sub(): Test if equal to test value, then subtractteq_then_rsb(): Test if equal to test value, then reverse subtracttne_then_write(): Test if not equal to test value, then writetne_then_add(): Test if not equal to test value, then addtne_then_sub(): Test if not equal to test value, then subtracttne_then_rsb(): Test if not equal to test value, then reverse subtracttge_then_write(): Test if greater than or equal to test value, then writetge_then_add(): Test if greater than or equal to test value, then addtge_then_sub(): Test if greater than or equal to test value, then subtracttge_then_rsb(): Test if greater than or equal to test value, then reverse subtracttgt_then_write(): Test if greater than test value, then writetgt_then_add(): Test if greater than test value, then addtgt_then_sub(): Test if greater than test value, then subtracttgt_then_rsb(): Test if greater than test value, then reverse subtracttle_then_write(): Test if less than or equal to test value, then writetle_then_add(): Test if less than or equal to test value, then addtle_then_sub(): Test if less than or equal to test value, then subtracttle_then_rsb(): Test if less than or equal to test value, then reverse subtracttlt_then_write(): Test if less than test value, then writetlt_then_add(): Test if less than test value, then addtlt_then_sub(): Test if less than test value, then subtracttlt_then_rsb(): Test if less than test value, then reverse subtracttgele_then_write(): Test if old value is in closed interval[l,r], then writetgele_then_add(): Test if old value is in closed interval[l,r], then addtgele_then_sub(): Test if old value is in closed interval[l,r], then subtracttgele_then_rsb(): Test if old value is in closed interval[l,r], then reverse subtracttgelt_then_write(): Test if old value is in left-closed right-open interval[l,r), then writetgelt_then_add(): Test if old value is in left-closed right-open interval[l,r), then addtgelt_then_sub(): Test if old value is in left-closed right-open interval[l,r), then subtracttgelt_then_rsb(): Test if old value is in left-closed right-open interval[l,r), then reverse subtracttgtle_then_write(): Test if old value is in left-open right-closed interval(l,r], then writetgtle_then_add(): Test if old value is in left-open right-closed interval(l,r], then addtgtle_then_sub(): Test if old value is in left-open right-closed interval(l,r], then subtracttgtle_then_rsb(): Test if old value is in left-open right-closed interval(l,r], then reverse subtracttgtlt_then_write(): Test if old value is in open interval(l,r), then writetgtlt_then_add(): Test if old value is in open interval(l,r), then addtgtlt_then_sub(): Test if old value is in open interval(l,r), then subtracttgtlt_then_rsb(): Test if old value is in open interval(l,r), then reverse subtracttst_then_op(): Test usingtst()function, then operate usingop()function
- Bitmap array atomic operations:
xwbmpaop_c0i(): Clear bit i to 0xwbmpaop_s1i(): Set bit i to 1xwbmpaop_x1i(): Toggle bit ixwbmpaop_t1i(): Test if bit i is 1xwbmpaop_t0i_then_s1i(): Test if bit i is 0, then set it to 1xwbmpaop_t1i_then_c0i(): Test if bit i is 1, then clear it to 0xwbmpaop_ffs_then_c0i(): Find the first set bit from the least significant bit and clear it to 0xwbmpaop_ffz_then_s1i(): Find the first zero bit from the least significant bit and set it to 1xwbmpaop_fls_then_c0i(): Find the first set bit from the most significant bit and clear it to 0xwbmpaop_flz_then_s1i(): Find the first zero bit from the most significant bit and set it to 1
Lock-Free Queues
XWOS’s C library provides lock-free queue functions. The implementation of lock-free queues depends on the CPU’s atomic operation instructions.
- XWOS header file:
xwos/lib/lfq.h - Interface:
xwos/ospl/lfq.h - Implementation:
xwosimpl_soc_lfq.h
Spinlocks
In multi-core systems, memory regions shared by multiple CPUs need to be protected by spinlocks. The implementation of spinlocks depends on atomic operation instructions and memory barrier instructions.
- XWOS header files:
xwos/osal/lock/spinlock.h: Spinlockxwos/osal/lock/seqlock.h: Spinlock derivative lock, sequential lock
- Interface:
xwos/ospl/spinlock.h - Implementation:
xwosimpl_soc_spinlock.h
Interrupts
- XWOS header file:
xwos/osal/irq.h - Interface:
xwos/ospl/irq.h: Defines functions that the BSP needs to adapt;
- Implementation:
xwosimpl_irq.h: Implements the functions defined in the XWOS porting layer;
- Interrupt numbers:
- XWOS defines the interrupt number type
xwirq_t, which is a signed number: - Positive integers and 0: Represent SoC peripheral interrupts;
- Negative numbers: Represent exceptions.
- XWOS defines the interrupt number type
- Interrupt priority requirements
The context switching interrupt is the lowest priority interrupt in the system
Context switching interrupt <= Tick timer interrupt <= Scheduler service interrupt
- Functions that must be provided in the OS porting layer:
void xwospl_cpuirq_enable_lc(void): Enable local CPU interruptsvoid xwospl_cpuirq_disable_lc(void): Disable local CPU interruptsvoid xwospl_cpuirq_restore_lc(xwreg_t cpuirq): Restore local CPU interruptsvoid xwospl_cpuirq_save_lc(xwreg_t * cpuirq): Save then disable local CPU interruptsbool xwospl_cpuirq_test_lc(void): Test local CPU interrupt statusxwer_t xwospl_irq_get_id(xwirq_t * irqnbuf): Get the current interrupt number, also used for determining contextxwer_t xwospl_irq_enable(xwirq_t irqn): Enable a specific peripheral interruptxwer_t xwospl_irq_disable(xwirq_t irqn): Disable a specific peripheral interruptxwer_t xwospl_irq_save(xwirq_t irqn, xwreg_t * flag): Save a specific peripheral interrupt’s enabled state, then disable itxwer_t xwospl_irq_restore(xwirq_t irqn, xwreg_t flag): Restore a specific peripheral interrupt’s enabled state
Hardware Timer
Each CPU requires a private hardware timer to provide tick interrupts. XWOS’s scheduling, timeout, and software timers are all based on tick interrupts.
- Interface:
xwos/ospl/syshwt.h - Implementation:
xwosimpl_syshwt.h - Interface functions:
xwospl_syshwt_init(): Initialize the hardware timerxwospl_syshwt_start(): Start the hardware timerxwospl_syshwt_stop(): Stop the hardware timerxwospl_syshwt_get_timeconfetti(): Return how many nanoseconds until the next timer interrupt
Scheduler
- Interface:
xwos/ospl/skd.h - Implementation:
xwosimpl_skd.h - Interface functions:
xwospl_skd_init(struct xwospl_skd * xwskd): Initialize the schedulerxwospl_skd_init_stack(): Initialize the scheduler object (thread) stackxwospl_skd_get_id(): Get the current CPU IDxwospl_skd_start(): Start the schedulerxwospl_skd_suspend(): Suspend the scheduler, for power managementxwospl_skd_resume(): Resume the scheduler, for power managementxwospl_skd_req_swcx(): Request schedulingxwospl_skd_isr_swcx(): Context switching interruptxwospl_thd_exit_lc(): Thread exit on the current CPUxwospl_thd_freeze_lc(): Freeze the currently running thread on the current CPUxwospl_thd_outmigrate(): Migrate a thread out of another CPU and prepare to migrate it to another CPU (multi-core only)xwospl_thd_immigrate(): Migrate a thread to a target CPU (multi-core only)
Linker Script
The SoC Description Layer includes the SoC’s basic linker script. When using it, a XuanWuOS.lds must be defined in the cfg folder of the board directory,
which contains the definition of the SoC’s address space, and then includes the linker script from the SoC Description Layer.
For example: xwbd/WeActH750/cfg/XuanWuOS.lds only defines MEMORY and include xwcd/soc/arm/v7m/gcc/m7/stm32/h7.lds.
- XWOS defines some sections. During linking, kernel code and kernel data can be placed in specific regions of the image file.
This requires specifying in the linker script how these sections should be placed.
__xwos_init_code: Initialization code, placed in the .xwos.init.text section__xwos_init_rodata: const data during the initialization phase, placed in the .xwos.init.rodata section__xwos_exit_code: Exit code, placed in the .xwos.exit.text section__xwos_exit_rodata: const data during the exit phase, placed in the .xwos.exit.rodata section__xwos_ivt: Interrupt vector table, placed in the .xwos.ivt section__xwos_isr: Interrupt code, placed in the .xwos.isr.text section__xwos_bh: Interrupt bottom-half code, placed in the .xwos.isr.text section__xwos_code: XWOS kernel code, placed in the .xwos.text section__xwos_api: XWOS kernel API, placed in the .xwos.text section__xwos_rodata: const data, placed in the .xwos.rodata section__xwos_data: Global and static variables, placed in the .xwos.data section
- If these custom sections are not needed, the above macros can be defined as empty. Correspondingly, code will be placed in the default
.textsection, data in the.datasection, and const data in the.rodatasection. These three sections are generated by the compiler by default. - When
__xwos_datais defined as empty, the configurationXWKNCFG_RELOCATE_DATAincfg/xwos.hshould also be undefined or defined as0.
Initialization Flow
XWOS provides a universal Boot Flow:
flowchart LR
poweron("Power On") --> Low-Level Initialization Phase --> System Initialization Phase --> User Program
subgraph Low-Level Initialization Phase
direction TB
arch_lowlevel_init["arch_lowlevel_init()"] --> cpu_lowlevel_init
cpu_lowlevel_init["cpu_lowlevel_init()"] --> soc_lowlevel_init
soc_lowlevel_init["soc_lowlevel_init()"] --> board_lowlevel_init
board_lowlevel_init["board_lowlevel_init()"]
end
subgraph System Initialization Phase
direction TB
xwos_init["xwos_init()"] --> arch_relocate
arch_relocate["arch_relocate()"] --> arch_init
arch_init["arch_init()"] --> cpu_init
cpu_init["cpu_init()"] --> soc_init
soc_init["soc_init()"] --> board_init
end
subgraph User Program
direction LR
subgraph "xwos_main()"
direction LR
skd["Start Scheduler"]
thd["Thread Initialization"]
device["Device Driver Initialization"]
libc["C/C++ Standard Library Initialization"]
lua["Lua VM Initialization"]
end
end
- Users can insert SoC initialization code at appropriate points in the flow, but note:
- Global variables cannot be accessed during the lowlevel_init flow because the initial values of global variables have not yet been copied from flash to RAM;
- C++ code can only be called after cxx_init;
- In XWOS’s initialization flow, the interrupt controller and scheduler are initialized in
soc_init(). If the user does not use XWOS’s initialization flow, the following must be called in order:xwos_init(): Initialize the XWOS kernel;- Multi-core system:
xwmp_irqc_construct(): Initialize the interrupt controller for each CPU;xwmp_irqc_register(): Register each CPU’s interrupt controller to the interrupt control subsystem;xwmp_skd_init_lc(): Run this function once on each CPU to initialize its own scheduler;
- Single-core system:
xwup_irqc_init(): Initialize the interrupt controller;xwup_skd_init_lc(): Initialize the scheduler;
Build Integration Environment
XWOS provides a Build System that can run on Windows and Linux. Users can choose to use XWOS’s build integration environment or use other IDEs for building.
Using the XWOS Build System
- XWOS’s build system independently compiles the kernel, xwmd modules, xwcd modules, xwem modules, xwam modules, and OEM modules into static libraries .a, and then links them together. The compilation configuration (header files, compiler options) for each module is completely independent, which can be understood as different sub-projects.
- The build starts by executing the
makecommand from thexwbd/board_name/directory.
Using Other IDE Build Systems
- Required header file search paths:
- XWOS root directory
XWOS - Architecture Description Layer (ADL) directory: e.g., for ARMv7m,
xwcd/soc/arm/v7m/gcc - CPU Description Layer (CDL) directory: e.g., for ARMv7m7,
xwcd/soc/arm/v7m/gcc/m7 - SoC Description Layer (SDL) directory: e.g., for STM32H7,
xwcd/soc/arm/v7m/gcc/m7/stm32h7x - Board directory: e.g., for the
WeActMiniStm32H750board,xwbd/WeActMiniStm32H750
- XWOS root directory
- Required source files:
- Kernel directory
xwos - Architecture Description Layer (ADL) directory: e.g., for ARMv7m,
xwcd/soc/arm/v7m/gcc - CPU Description Layer (CDL) directory: e.g., for ARMv7m7,
xwcd/soc/arm/v7m/gcc/m7 - SoC Description Layer (SDL) directory: e.g., for STM32H7,
xwcd/soc/arm/v7m/gcc/m7/stm32h7x - Board directory: e.g., for the WeActH750 board,
xwbd/WeActH750 - Middleware
xwmd, driver frameworkxwcd/ds, third-party modulesxwem, application modulesxwamare not mandatory. If only the XWOS kernel is used, these can be removed.
- Kernel directory
- If the other IDE’s toolchain is not gcc, the
xwosimplcode in ADL, CDL, and SDL must be re-implemented. In this case, the code inxwcd/socis also not needed. - Configuration needs to be modified:
xwbd/WeActMiniStm32H750/cfg. - In the
xwbd/WeActMiniStm32H750directory, executemake cfgonce to generate, then copyxwbd/WeActMiniStm32H750/wkspc/autogen.htoxwbd/WeActMiniStm32H750/cfg. - The IDE’s linker script needs to be configured.